This invention relates generally to differential amplifiers and more particularly to differential amplifiers having a pair of input transistors.
As is known in the art, differential amplifiers have been used in a wide variety of applications including use in the input stage of operational amplifiers. One such differential amplifier includes a pair of input transistors having first electrodes coupled to a common current source, second electrodes providing a pair of inputs for the differential amplifier, and third electrodes coupled either directly to passive resistive loads, or indirectly to such passive resistive loads through an active current mirror circuit to provide an output for the differential amplifier. Such differential amplifiers may include as the input transistors thereof either bipolar transistors or field effect transistors. When bipolar transistors are used, the base electrodes provide the pair of inputs for the differential amplifier with typically the emitter electrodes being connected to the common current source. When field effect transistors are used as the input transistors, the gate electrodes provide the pair of input electrodes and typically the source electrodes are connected to the common current source. In either case, when such differential amplifier is used as the input stage of an operational amplifier, mismatches in the voltages between the base and emitter electrodes (i.e. V.sub.be) in the case of bipolar transistors or in the voltages between the gate and source electrodes (i.e. V.sub.gs) in the case of field effect transistors, result in an undesirable temperature sensitive offset voltage being produced at the output of the operational amplifier (such offset voltage being defined as the voltage required at the pair of input terminals from a zero source impedance to drive the output voltage produced by the operational amplifier to zero volts). It is further noted that since the offset voltage is inversely related to the transconductance of the transistors and since the transconductance of field effect transistors is an order of magnitude lower than the transconductance of bipolar transistors, while it is important to reduce V.sub.be mismatches in bipolar transistors, it is even more critical to reduce the effect of mismatching in V.sub.gs in field effect transistors.
As is also known, the V.sub.be of a bipolar transistor is a function of the emitter area and doping concentration while the V.sub.gs of a field effect transistor is a function of gate channel dimensions and doping concentration. Thus, during wafer fabrication, emitter areas, channel dimensions and doping concentrations are controlled and are matched for the pair of input transistors as far as possible to provide a pair of matched input transistors. However, despite this fabrication process control the input transistors may have dimensions and/or doping concentration mismatches. Various techniques suggested to compensate for these fabrication process mismatches include the injecting of a compensating current directly into the passive resistive loads so that the voltages at the outputs of the differential amplifier are equal at the quiescent operating point, i.e. when both transistors pass equal amounts of current produced by the current source. With one technique, a pair of current sources are provided to inject compensating currents into both passive resistive loads, the amount of current injected into each one of the loads being adjusted by trimmable resistors. While such technique may be useful in some applications, imbalances in the compensating currents over the operating range of temperatures because of temperature changes in the trimmed resistors will generally result in concomitant imbalances over the operating range of temperatures. In other one of such techniques, here when an active current mirror is used between the pair of resistive loads and the outputs of the differential amplifier, a single compensating current is injected directly into one of the passive resistive loads. With such arrangement, because the injected current introduces an error in the match of the currents in the current mirror and while balanced at one temperature the balance is not maintained over a relatively wide range of operating temperatures. Thus, the control circuit suggested to direct the injected amount to the proper one of the pair of resistive loads causes an error uncertainty and imbalance of the desired balanced current mirror transistors over a wide range of temperatures.